This invention relates, in general, to processing within a computing environment, and in particular, to facilitating memory accesses within such an environment.
Efficient memory access is important to the overall performance of a computing environment. Since physical memory is of a finite size, in many computing environments, virtual addresses are used to reference memory, allowing use of a larger address range than is physically available. Those virtual addresses are then translated from virtual addresses to absolute addresses, which correspond directly to physical locations in memory.
To translate a virtual address to an absolute address, various operations may be used. As one example, in computer architectures that implement hierarchical page tables, a page walk of the hierarchical page tables is performed to locate the absolute address corresponding to the virtual address. In another example in which the computer architecture uses inverted page tables, a hashtable lookup of the inverted page tables is performed to locate the absolute address corresponding to the virtual address. These operations are very expensive, and since address translations are very common, these operations often have an impact on system performance.
In an effort to reduce this impact on performance, techniques have been employed to improve address translation. Once such technique includes the use of a translation lookaside buffer (TLB), which caches the results of recent translations. This buffer is consulted before, for instance, a page walk is performed, and if an entry is found for the desired virtual address, it provides a direct mapping to the corresponding absolute address. This avoids repeating expensive page walks for commonly used translations, thereby improving performance.